In many networking applications, such as industrial Ethernet, maintaining and monitoring the quality of a data link is an important issue. It is very desirable to know when a digital signal processor that recovers data in an Ethernet physical layer device is operating within its proper parameters. Changes in the operating parameters could indicate a degradation in the link quality. Notifying the system of potential issues in the cabling may allow network administrators to detect potential issues before they become critical and cause failure of the network.
The present invention will be described with reference to an exemplary Ethernet physical layer device. It is understood, however, that the principles of the present invention are not limited to the exemplary network embodiment described in this patent document.
The operation of a physical layer device is described in an IEEE publication entitled “IEEE Standards for Local and Metropolitan Area Networks: Media Access Control (MAC) Parameters, Physical Layer, Medium Attachment Units, and Repeater for 100 Mb/s Operation, Type 100BASE-T.” The short name of this standard is IEEE Standard 802.3. The Physical Medium Dependent (PMD) sublayer for 100BASE-TX is defined in “Fibre Distributed Data Interface (FDDI)— Token Ring Twisted Pair Physical Layer Medium Dependent (TP-PMD)” (ANSI X3.263: 1995). The TP-PMD document provides the specification for receiving signaling on the physical medium and converting it to the digital representation required by the Physical Medium Attachment (PMA) and Physical Coding (PCS) sublayers. A commonly used method of implementing the Twisted Pair PMD sublayer utilizes a Digital Signal Processor (DSP) to recover the data and clock from the physical layer signaling.
There is a need in the art for a system and method that is capable of monitoring the quality of a data link in a 100 Mb Ethernet physical layer device. In particular, there is a need in the art for a system and method that is capable of monitoring data link parameters in a digital signal processor that recovers data in an Ethernet physical layer device.
In order to better understand the advance in the art that the present invention provides, a prior art Ethernet system will be first described. FIG. 1 illustrates a block diagram 100 of a prior art Ethernet system. FIG. 1 shows the basic components of a single Ethernet capable device connected to a physical cable. The device comprises a Media Access Controller (“Ethernet MAC 11”) that is capable of sending and receiving packetized data through an Ethernet physical layer device 12 (“Ethernet PHY 12”) to a physical medium such as a Category 5 Cable (“Cat5 Cable 13”). The Ethernet MAC 11 sends and receives packetized data across the MAC Data Interface. The MAC Data Interface may be either a Media Independent Interface (“MII”) or a Reduced Media Independent Interface (“RMII”). The Ethernet MAC 11 controls the Ethernet PHY 12 and monitors its status through a Management Interface (designated “Mgmt Interface” in FIG. 1).
The Ethernet PHY 12 also requires a clock source 14. The clock source 14 comprises a twenty five megaHertz (25 MHz) clock when an MII interface is used. The clock source 14 comprises a fifty megaHertz (50 MHz) clock when an RMII interface is used. In addition, the Ethernet PHY 12 may comprise status light emitting diodes 15 (“Status LEDs 15”) in order to externally provide visible indication of the status of the Ethernet PHY 12.
The Ethernet PHY 12 is connected to the Cat5 Cable 13 through a Magnetics unit 16 and an RJ-45 Connector 17. For simplicity and clarity, the Magnetics unit 16 and the RJ-45 Connector 17 will not be shown in subsequent figures.
FIG. 2 illustrates a block diagram of a prior art Ethernet Receive Phy 150 and Receive Mac 120. The data that is received from Category 5 cable 140 is provided to a Receive (RX) Physical Media Dependent (PMD) block 200. PMD block 200 comprises analog front end 205 and digital signal processor 210. Analog front end 205 converts the analog signals from Category 5 cable 140 into a digital form and provides the digital form of the analog signals to digital signal processor 210. Digital signal processor 210 processes the digital form of the data and recovers the transmitted data and clock signals.
As described in the IEEE Standard 802.3, the data is then sequentially provided to a Physical Medium Attachment (PMA) sublayer 215, a Physical Coding Sublayer (PCS) 220, and Media Access Controller (MAC) data interface unit 225. The MAC data interface unit 225 is capable of operating either in Media Independent Interface (MII) mode or in Reduced Media Independent Interface (RMII) mode. The MAC data interface unit 225 provides the received data to the Media Access Controller 120. As indicated in FIG. 2, Media Access Controller 120 may comprise a microprocessor unit (MPU) or a central processing unit (CPU).
The Ethernet Receive Phy 150 comprises a set of management registers in Register Block 230. The management registers are used by the Media Access Controller 120 to control the Ethernet Receive Phy 150 and to monitor the status of its operation. The management interface is commonly provided through a serial management interface defined in Clause 22 of the IEEE 802.3 specification. In addition, the Ethernet Receive Phy 150 shown in FIG. 2 is capable of providing an interrupt signal to the Media Access Controller 120.
As previously mentioned, there is a need in the art for a system and method that is capable of monitoring the quality of a data link in a 100 Mb Ethernet physical layer device and that is capable of monitoring data link parameters in a Ethernet digital signal processor.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
The term “controller” means any device, system, or part thereof that controls at least one operation. A controller may be implemented in hardware, software, firmware, or combination thereof. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.